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CS61318
E1 Line Interface Unit
Features
s E1 Line Interface Unit s No Crystal Needed for Jitter Attenuation s Meets CTR-12/TBR-12 Jitter Tolerance and Attenuation Requirements s Meets ITU-T G.775 Requirements for LOS and AIS s Meets the BS6450 Transmitter Short-Circuit Requirements for E1 Applications s AWG for User Programmable Pulse Shapes s Line Quality Monitoring Function s TX Driver High Impedance / Low Power Control s AIS and LOS Monitoring s Generation and Detection of Loop Up / Loop Down Signaling s Selectable HDB3 Encoding/Decoding s Selectable Unipolar or Bipolar I/O s Compliant with:
-- ITU-T Recommendations: G.703, G.732, G.775, I.431 -- ETSI ETS 300 011, 300 233, CTR 12, TBR 13 -- TR-NET-00499
Description
The CS61318 is an E1 primary rate line interface unit. This device combines the complete analog transmit and receive circuitry for a single, full-duplex interface E1 rates. The device provides jitter attenuation compliant to CTR12/TBR13 without requiring an external crystal. Also, the CS61318 is pin and function compatible with the Level One LXT318. In addition to a basic hardware control mode, a host mode is available that gives the user an enhanced functionality via a serial microprocessor interface. The extended features include custom pulse shape generation, AIS and LOS monitoring functions, signal strength monitoring, and generation and detection of loop up and loop down codes.
ORDERING INFORMATION CS61318-IL CS61318-IP
28-pin PLCC 28-pin PDIP
TCLK TDATA/TPOS UBS/TNEG JASEL
2
3
4 11
E N C O D E R
JITTER ATTEN
TRANSMIT TIMING & CONTROL
PULSE SHAPING CIRCUITRY ROM / RAM
13
LINE DRIVERS
TTIP
16 28 26
TRING CLKE/TAOS CS/RLOOP SCLK/LLOOP SDI/LBO1 SDO/LBO2
TAOS Enable REMOTE LOOPBACK LOCAL LOOPBACK (DIGITAL) REGISTERS & CONTROL LOGIC LOS/ NLOOP Clear RCLK RDATA/RPOS
BPV/RNEG
SERIAL PORT
27 24 25
LLOOP Enable EQUALIZER CONTROL SLICERS & PEAK DETECT NOISE & CROSSTALK FILTERS
D 8E C 7O D 6 E R
LOCAL LOOPBACK (ANALOG) 18 LATN
JITTER ATTEN
TIMING & DATA RECOVERY
MAGNITUDE EQUALIZER
AGC
19 20
RTIP
RRING
INT/NLOOP LOS
23 12
INBAND NLOOP & LOS PROCESSOR
RECEIVE CLOCK GENERATOR
1
MCLK
9 XTALIN
10 XTALOUT
5 MODE
21 RV+
22
14
15 TV+
RGND TGND
Preliminary Product Information
P.O. Box 17847, Austin, Texas 78760 (512) 445 7222 FAX: (512) 445 7581 http://www.cirrus.com
This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice.
Copyright (c) Cirrus Logic, Inc. 1999 (All Rights Reserved)
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TABLE OF CONTENTS
1 CHARACTERISTICS AND SPECIFICATIONS ......................................................................... 4 ABSOLUTE MAXIMUM RATINGS ........................................................................................... 4 RECOMMENDED OPERATING CONDITIONS ....................................................................... 4 DIGITAL CHARACTERISTICS ................................................................................................. 4 ANALOG SPECIFICATIONS .................................................................................................... 5 E1 SWITCHING CHARACTERISTICS ..................................................................................... 6 SERIAL PORT SWITCHING CHARACTERISTICS.................................................................. 7 2 THEORY OF OPERATION ........................................................................................................ 8 2.1 Operating Modes ............................................................................................................... 8 2.2 Master Clocks .................................................................................................................... 8 2.3 Transmitter ......................................................................................................................... 8 2.4 Transmit All Ones Select ................................................................................................... 9 2.4.1 Receiver ................................................................................................................ 9 2.4.2 Clock Recovery ..................................................................................................... 9 2.4.3 Jitter Tolerance ..................................................................................................... 9 2.4.4 Receiver Line Attenuation Indication ..................................................................... 9 2.5 Jitter Attenuator ................................................................................................................. 9 2.6 Receiver Loss of Signal ................................................................................................... 10 2.7 Local Loopback ................................................................................................................ 10 2.8 Remote Loopback ............................................................................................................ 11 2.9 Network Loopback ........................................................................................................... 11 2.10 Alarm Indication Signal .................................................................................................. 11 2.11 Serial Interface ............................................................................................................... 11 2.11.1 Control Register 1: Address 0x10 ............................................................................... 13 2.11.2 Control Register 2: Address 0x11 ............................................................................. 14 2.11.3 Equalizer Gain (EQGAIN): Address 0x12 ................................................................... 14 2.11.4 Arbitrary Waveform RAM Address (RAM): Address 0x13 .......................................... 14 2.12 Interrupts ........................................................................................................................ 15 2.13 Power On Reset / Reset ................................................................................................ 15 2.14 Power Supply ................................................................................................................. 15 3 ARBITRARY WAVEFORM GENERATION ............................................................................. 16 4 PIN DESCRIPTION .................................................................................................................. 19 4.1 Power Supplies ................................................................................................................ 20 4.2 Oscillator .......................................................................................................................... 20 4.3 Control ............................................................................................................................. 20 4.4 Status ............................................................................................................................... 21 4.5 Serial Control Interface .................................................................................................... 21 4.6 Data Input/Output ............................................................................................................ 22 5 PACKAGE DIMENSIONS ........................................................................................................ 24 6 APPLICATIONS ....................................................................................................................... 26 Contacting Cirrus Logic Support For a complete listing of Direct Sales, Distributor, and Sales Representative contacts, visit the Cirrus Logic web site at: http://www.cirrus.com/corporate/contacts/
Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Items from any Cirrus Logic website or disk may be printed for use by the user. However, no part of the printout or electronic files may be copied, reproduced, stored in a retrieval system, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise) without the prior written consent of Cirrus Logic, Inc. Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners which may be registered in some jurisdictions. A list of Cirrus Logic, Inc. trademarks and service marks can be found at http://www.cirrus.com.
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LIST OF FIGURES
Figure 1. Signal Rise and Fall Characteristics ................................................................. 6 Figure 2. Recovered Clock and Data Switching Characteristics ...................................... 6 Figure 3. Transmit Clock and Data Switching Characteristics ......................................... 6 Figure 4. Serial Port Write Timing Diagram ..................................................................... 7 Figure 5. Serial Port Read Timing Diagram ..................................................................... 7 Figure 6. Mask of the Pulse at the 2048 kbps Interface ................................................... 8 Figure 7. LATN Pulse Width encoding ........................................................................... 10 Figure 8. Typical Jitter Transfer Function ....................................................................... 10 Figure 9. Input/Output Timing (showing address 0x10) ................................................. 12 Figure 10. Phase Definition of Arbitrary Waveform ........................................................ 16 Figure 11. Example of Summing of Waveforms ............................................................. 16 Figure 12. CS61318 Host Mode Operation .................................................................... 26 Figure 13. Hardware Mode Configuration ..................................................................... 27
LIST OF TABLES
Table 1. Data Output/Clock Relationship ........................................................................... 9 Table 2. Register Map..................................................................................................... 12 Table 3. Control Register 1 (0x10) Decoding................................................................... 15 Table 4. CS61318 Diagnostic Mode Availability .............................................................. 17 Table 5. Transformer Specification .................................................................................. 18 Table 6. Recommended Tranformers for the CS61318 ................................................... 18
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1 CHARACTERISTICS AND SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS WARNING: Operation
Parameter DC Supply Input Voltage, Any Pin Input Current, Any Pin Ambient Operating Temperature Storage Temperature (Note 1) (referenced to RGND=TGND=0 V) Symbol RV+ TV+ Vin Iin TA Tstg
at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Min RGND-0.3 -10 -40 -65 Max 6.0 (RV+) + 0.3 (RV+) + 0.3 10 85 150 Units V V V mA C C
Notes: 1. Transient currents of up to 100 mA will not cause SCR latch-up. Also TTIP, TRING, TV+ and TGND can withstand a continuous current of 100 mA.
RECOMMENDED OPERATING CONDITIONS
Parameter DC Supply Ambient Operating Temperature Power Consumption, Long Haul Power Consumption, Short Haul (Notes 3,4,5) (Notes 3,4,5) Symbol (Note 2) RV+, TV+ TA PC PC Min 4.75 -40 Typ 5.0 25 390 480 Max 5.25 85 630 710 Units V C mW mW
Notes: 2. TV+ must not exceed RV+ by more than 0.3 V. 3. Power consumption figures assume device is driving line load over operating temperature range. The consumption of both the IC and the load are included. Digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pF capacitive load. 4. Typical consumption corresponds to 50% ones density and medium line length at 5.0 V. 5. Maximum consumption corresponds to 100% ones density and maximum line length at 5.25 V.
DIGITAL CHARACTERISTICS (TA = -40C to 85C; TV+, RV+ = 5.0 V 5%; GND = 0 V)
Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage IOUT = -40 A Low-Level Output Voltage IOUT = 1.6 mA Input Leakage Current (Note 6) PINS 1-4, 24-28 (Note 6) PINS 1-4, 24-28 (Notes 6, 7) PINS 6-8, 25 (Notes 6, 7) PINS 6-8, 25 Symbol VIH VIL VOH VOL Min 2.0 2.4 Typ Max 0.8 0.4 10 Units V V V V A
Notes: 6. This specification guarantees TTL compatibility (VOH = 2.4 V @ IOUT = -40 A). 7. Output drivers are TTL compatible and will drive CMOS logic levels into a CMOS load.
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ANALOG SPECIFICATIONS (TA = -40C to 85C; TV+, RV+ = 5.0 V 5%; GND = 0 V)
Parameter Transmitter AMI Output Pulse Amplitudes (Note 8) E1, 75 (Note 9) E1, 120 (Note 10) Low Z, Long Haul (Notes 11,12) 10 Hz - 8 kHz 8k Hz - 40 kHz 10 Hz - 40 kHz Broad Band (Notes 8, 12) (Notes 8, 13) -36 48 -15 430 (Note 14) (Note 15) 10 kHz - 100 kHz (Note 12, 15) 2 kHz (Note 12, 15) 10 Hz and below 10 kHz - 100 kHz (Note 12, 15) 1 Hz 45 160 0.35 6.0 300 0.35 138 2.14 2.7 2.37 3.0 1.5 0.015 0.015 0.015 0.020 0.2 20k -42 50 175 0.5 50 55 190 2.6 3.3 V V UI UI UI UI dB mA RMS dB mV dB mV dB % of peak bits UI UI UI UI UI Min Typ Max Units
Transmitter Output Impedance Transformer turns ratio = 1:2 Jitter Added by the Transmitter
Positive to Negative Pulse Imbalance Transmitter Short Circuit Current Receiver RTIP/RRING Input Impedance Sensitivity Below DSX (0 dB = 3.0 V)
Sensitivity Below G.703 (0 dB = 2.4 V) E1 - Short Haul Loss of Signal Threshold Data Decision Threshold Allowable Consecutive Zeros before LOS Receiver Input Jitter Tolerance - Short Haul
Receiver Input Jitter Tolerance - Long Haul
Notes: 8. Using a 0.47 F capacitor in series with the primary of a transformer recommended in the Applications Section. 9. Pulse amplitude measured at the secondary of the transformer across a 75 load. 10. Pulse amplitude measured at the secondary of the transformer across a 120 load. 11. Assuming that jitter free clock is input to TCLK. 12. Not production tested. Parameters guaranteed by design and characterization. 13. Measured broadband through a 0.5 resistor across the secondary of the transmitter transformer during the transmission of an all ones data pattern. 14. Data decision threshold established after the receiver equalizer filters pulse overshoot and undershoot. 15. Jitter tolerance for 0 dB input signal level. Jitter tolerance increases at lower frequencies.
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E1 SWITCHING CHARACTERISTICS (TA = -40C to 85C; TV+, RV+ = 5.0 V 5%;
GND = 0 V; Inputs: Logic 0 = 0 V, Logic 1 = RV+; See Figures 1, 2, & 3) Parameter TCLK Frequency TCLK Duty Cycle MCLK Frequency RCLK Duty Cycle Rise Time, All Digital Outputs Fall Time, All Digital Outputs TPOS/TNEG to TCLK Falling Setup Time TCLK Falling to TPOS/TNEG Hold Time RPOS/RNEG Valid Before RCLK Falling RPOS/RNEG Valid Before RCLK Rising RPOS/RNEG Valid After RCLK Falling RPOS/RNEG Valid After RCLK Rising (Note 19) (Note 20) (Note 19) (Note 20) (Note 16) (Note 18) (Note 19) Symbol ftclk (Note12) tpwh2/tpw2 fmclk tr tf tsu2 th2 tsu1 tsu1 th1 th1 (Note 17) tpwh1/tpw1 Min 40 45 25 25 100 100 100 100 Typ 2.048 50 2.048 50 194 194 194 194 Max 60 55 85 85 Units MHz % MHz % ns ns ns ns ns ns ns ns
Notes: 16. MCLK provided by an external source to TCLK. 17. RCLK duty cycle will be 62.5% or 37.5% when jitter attenuator FIFO limits are reached. 18. At max load of 1.6mA and 50pF. 19. Host Mode (CLKE = 1). 20. Host Mode (CLKE = 0).
tr 90% 10% 90% 10% tf
Any Digital Output
Figure 1. Signal Rise and Fall Characteristics
tpw1
RCLK (CLKE = 1)
t pwl1 t su1
t pwh1 t h1
RPOS RNEG
(CLKE = 0)
RCLK
Figure 2. Recovered Clock and Data Switching Characteristics
t pw2 t pwh2 TCLK t su2 TPOS/TNEG t h2
Figure 3. Transmit Clock and Data Switching Characteristics
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SERIAL PORT SWITCHING CHARACTERISTICS (TA = -40 to 85C; TV+, RV+ = 5V 5%;
Inputs: Logic 0 = 0 V, Logic 1 = RV+) Parameter SDI to SCLK Setup Time SCLK to SDI Hold Time SCLK Low Time SCLK High Time SCLK Rise and Fall Time CS to SCLK Setup Time SCLK to CS Hold Time CS Inactive Time SCLK to SDO Valid CS to SDO High Z Notes: 21. Output load capacitance = 50 pF
t cwh CS t cc SCLK t ch t cl t cch
Symbol tdc tcdh tcl tch tr, tf tcc tcch tcwh (Note 21) tcdv tcdz
Min 50 50 240 240 50 50 250 -
Typ 100
Max 50 200 -
Units ns ns ns ns ns ns ns ns ns ns
t dc
SDI LSB CONTROL
t cdh LSB BYTE DATA BYTE
t cdh MSB
Figure 4. Serial Port Write Timing Diagram
CS
SCLK
SDI
LAST ADDR BIT
t cdv SDO CLKE = 0 t cdv
D0 D1 D6 D7
t cdz
HIGH Z SDO CLKE = 1
D0 D1 D6 D7
Figure 5. Serial Port Read Timing Diagram
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2 THEORY OF OPERATION
The CS61318 E1 Line Interface is a fully integrated transceiver designed for 2.048 Mbps E1 operation. The device provides an interface to twisted pair or co-axial media through standard pulse transformers and matching resistors. For added flexibility, the device can be controlled through a serial microprocessor interface (Host Mode Operation) or via device pins (Hardware Mode).
Percent of nominal peak voltage 120 110 244 ns 194 ns 269 ns
100
90 80
2.1
Operating Modes
50
The CS61318 can be controlled in stand-alone hardware interface mode (MODE pin is low), or by a microcontroller in serial host mode (MODE pin is high). Additional functionality is available in the host mode as described in the Serial interface section.
10 0 -10 -20 219 ns 488 ns
Nominal Pulse
2.2
Master Clocks
The CS61318 requires a reference clock for the receiver and the jitter attenuator. A 2.048 MHz external clock can be input to MCLK, or a 4x crystal can be connected to the on-chip oscillator. This frequency reference should be within +50 ppm of the nominal operating frequency. Jitter and wander on the reference clock will degrade jitter attenuation and receiver jitter tolerance. If MCLK is provided, the crystal oscillator is ignored.
Figure 6. Mask of the Pulse at the 2048 kbps Interface
2.3
Transmitter
The CS61318 drives a 75 or 120 line through the appropriate transformer and matching resistors. A summary of transformer and resistor configurations is given in the Applications section at the end of this datasheet. Using the recommended circuits will produce E1 pulses compliant to the G.703 template shown in Figure 6. Custom transmit pulse shapes may be implemented by writing pulse shape coefficients to on-board pulse shape registers. Custom pulses may be used to correct for pulse shape degradation or distortion caused by improper termination, suboptimal interconnect wiring, or loading from external components such as high voltage protection devices. Use of this feature is described in the Arbitrary Waveform Generation section. The CS61318 will detect the absence of TCLK, and will force TTIP and TRING to high impedance after 175 bit periods, preventing transmission when
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The transmitter accepts digital E1 input data and drives appropriately shaped AMI (Alternate Mark Inversion) pulses onto a transmission line through a transformer. The transmit data (TPOS & TNEG or TDATA) is sampled on the falling edge of the input clock, TCLK. Tying TNEG high for more than 16 TCLK cycles enables unipolar I/O mode. This changes TPOS to TDATA, RPOS to RDATA, and RNEG to BPV. In this mode the HDB3 encoder and decoder is enabled on both the receive and transmit paths.
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data input is not present. In host mode, the transmitter can be set to high impedance by setting the TxHIZ bit, CR2.1, to "1." When any transmit control bit (TAOS or LLOOP) is toggled, the transmitter outputs will require approximately 22 bit periods to stabilize. The transmitter will take longer to stabilize when RLOOP is selected because the timing circuitry must adjust to the new frequency. Data on RPOS and RNEG (RDATA), is stable and may be latched using the falling edge of recovered clock, RCLK. In host mode, CLKE, pin 28, determines the clock polarity for which output data is stable and valid as shown in Table 1. When CLKE is high, RPOS and RNEG (RDATA) are valid on the falling edge of RCLK. When CLKE is low, RPOS and RNEG are valid on the rising edge of RCLK.
MODE (pin 5) LOW HIGH CLKE Clock Edge for DATA CLOCK (pin 28) Valid Data Don't Care LOW RPOS RNEG RPOS RNEG SDO RPOS RNEG SDO RCLK RCLK RCLK SCLK RCLK RCLK SCLK Rising Rising Rising Falling Falling Falling Rising
2.4
Transmit All Ones Select
The transmitter provides for all ones insertion at the frequency of TCLK. If TCLK is absent, then MCLK is used (or the quartz crystal generated frequency in the absence of MCLK). Transmit all ones is selected when TAOS, pin 28, (CR1.7 = 1, in host mode) goes high, and causes continuous ones to be transmitted on the line (TTIP and TRING). When TAOS is active, the TPOS and TNEG (TDATA) inputs are ignored. If Remote Loopback is in effect, any TAOS request will be ignored.
HIGH
HIGH
Table 1. Data Output/Clock Relationship
2.4.1
Receiver
2.4.3
Jitter Tolerance
The receiver extracts data and clock from the input signal and outputs clock and synchronized data. The Long Haul receiver can receive signals over the entire range down to -36dB at E1 rates. The incoming pulses are amplified, equalized and filtered before being fed to the comparator for peak detection, slicing and data recovery. The clock and data recovery circuit exceeds the jitter tolerance specifications of ITU-T G.823 and ETSI CTR12. The RTIP and RRING inputs are biased to an intermediate DC level and treat the input signal differentially.
The CS61318 has excellent jitter tolerance, accepting as much as 0.35UI of jitter from 10 kHz to 100 kHz without error.
2.4.4
Receiver Line Attenuation Indication
2.4.2
Clock Recovery
The clock recovery circuit is a third-order phaselocked loop. The clock and data recovery circuit is tolerant of long strings of consecutive zeros, and will successfully receive a 1-in-175, jitter-free input signal.
The LATN pin, pin 18, outputs a coded signal that represents the signal level at the input of the receiver. As shown in Figure 7, the LATN output is measured against RCLK to provide the signal level in 7.5 dB increments. In host mode, the receive input signal level can be read from the Equalizer Gain register, address 0x12, to greater resolution, dividing the input range into 20 steps of 2 dB increments.
2.5
Jitter Attenuator
Jitter attenuation can be implemented in either the transmit (JASEL is low) or receive (JASEL is high)
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RCLK
LATN
1
2
3
4
5
LATN = 1 RCLK, 9.5 dB of Attenuation LATN = 2 RCLK, 1 9.5 dB of Attenuation LATN = 3 RCLK, 28.5 dB of Attenuation
LATN = 4 RCLK, 0 dB of Attenuation
Figure 7. LATN Pulse Width encoding
0 10 Attenuation in dB 20 30 40 50 CS61318 60 1 10
Minimum Attenuation Limit
ceived zeros are counted based on recovered clock cycles. When in the LOS state, received data is not output from RPOS/RNEG (RDATA); but is squelched until the device comes out of LOS. The LOS condition is exited using ITU-T G.775 criteria, namely 12.5% ones density for 175+/-75 bit periods with no more than 100 consecutive zeros. The receiver recovers signals down to -36 dB, and LOS will be declared below this signal level. In LOS, the RCLK frequency depends on whether MCLK is applied, and whether the jitter attenuator is in the transmit or receive path. If the jitter attenuator is in the receive path, the jitter attenuator will hold over the average incoming data frequency prior to LOS. RPOS (RDATA) and RNEG pins are forced low upon LOS. When the jitter attenuator is in the transmit path or not used, the clock recovery is referenced to MCLK, if provided, or the crystal oscillator. The frequency of RCLK in this case will simply remain slaved to the clock reference upon loss of data. The recovered clock remains as a 50% duty cycle clock.
Measured Performance 100 1k 10 k
Frequency in Hz
Figure 8. Typical Jitter Transfer Function
paths, or it can be eliminated from the circuit by setting the XTALIN, pin 9, high. The jitter attenuator on the CS61318 does not require a crystal, and can be activated by setting XTALIN, pin 9, low (preferred) or by floating pin 9. The jitter attenuator's corner frequency is approximately 1.25 Hz in order to comply with ETSI 300 011, CTR12, and recommendation I.431. A typical jitter attenuation graph is shown in Figure 8.
2.7
Local Loopback
2.6
Receiver Loss of Signal
The receiver will indicate loss of signal by setting LOS, pin 12 high (CR1.0 = 1 in host mode), upon power up, reset, when receiver gain is maximized, or upon receiving 175+/-15 consecutive zeros. Re10
Local loopback is selected by setting LLOOP, pin 27, high (CR1.6 = 1 in host mode). Selecting local loopback causes clock and data presented on TCLK, TPOS/TNEG (TDATA) to be output at RCLK, RPOS/RNEG (RDATA). Inputs to the transmitter are still transmitted on TTIP and
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TRING, unless TAOS has been selected, in which case AMI-encoded continuous ones are transmitted at the TCLK frequency. The receiver RTIP and RRING inputs are ignored when local loopback is in effect. NLOOP is temporarily suspended by LLOOP, but the NLOOP state is not reset.
2.10
Alarm Indication Signal
2.8
Remote Loopback
Remote loopback is selected by setting RLOOP, pin 26, high (CR1.5 = 1 in host mode). In remote loopback, the recovered clock and data input on RTIP and RRING are sent back out on the line via TTIP and TRING. Selecting remote loopback overrides a TAOS request. The recovered clock and data from the incoming signal are also sent to RCLK, RPOS and RNEG (RDATA). Note: simultaneous selection of local and remote loopback modes will cause a device reset to occur (see Reset).
The receiver sets the register bit, AIS, to "1" when less than 9 zeros are detected out of 8192 bit periods. AIS returns to "0" upon the first read after the AIS condition is removed, determined by 9 or more zeros out of 8192 bit periods.
2.11
Serial Interface
2.9
Network Loopback
In the Host Mode, pins 24 through 28 serve as a microcontroller interface. On-chip registers can be written to via the SDI pin or read from via the SDO pin at the clock rate determined by SCLK. Through these registers, a host controller can be used to control operational characteristics and monitor device status. The serial port read/write timing is independent of the system transmit and receive timing. Data transfers are initiated by taking the chip select input, CS, low (CS must initially be high). Address and input data bits are clocked in on the rising edge of SCLK. The clock edge on which output data is stable and valid is determined by CLKE as shown in Table 1. Data transfers are terminated by setting CS high. CS may go high no sooner than 50 ns after the rising edge of the SCLK cycle corresponding to the last write bit. For a serial data read, CS may go high any time to terminate the output and set SDO to high impedance. Figure 9 shows the timing relationships for data transfers when CLKE = 0. When CLKE = 1, data bit D7 is held until the falling edge of the 16th clock cycle. When CLKE = 0, data bit D7 is held valid until the rising edge of the 17th clock cycle. SDO goes high-impedance after CS goes high or at the end of the hold period of data bit D7. SDO goes to a high impedance state when not in use. SDO and SDI may be tied together in applications where the host processor has a bi-directional I/O port.
Network Loopback (automatic remote loopback) can be commanded from the network when the Network Loopback detect function is enabled. In Host Mode, Network Loopback (NLOOP) detection is enabled by writing ones to TAOS, LLOOP, and RLOOP, then clearing these three bits on a successive write cycle. In hardware mode, Network Loopback can be enabled by tying RLOOP to RCLK or by setting TAOS, LLOOP, and RLOOP high for at least 200 ns, and then low. Once enabled Network Loopback functionality will remain in effect until RLOOP is activated or the device is reset. When NLOOP detection is enabled, the receiver monitors the input data stream for the NLOOP data patterns (00001 = enable, 001 = disable). When an NLOOP enable data pattern is repeated for a minimum of five seconds (with less than 10E-3 BER), the device initiates a remote loopback. Once Network Loopback detection is enabled and activated by the NLOOP data pattern, the loopback is identical to Remote Loopback initiated at the device. NLOOP is reset if the disable pattern (001) is received for 5 seconds, or by activation of RLOOP.
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An address/command byte, shown in Figure 9, points to addresses 0x10 through 0x14 (address 0x10 shown), and precedes a data byte. The first bit of the address/command byte determines whether a read or a write is requested. The next six bits contain the address. The last bit is ignored. Data to the internal registers is input on the eight clock cycles immediately following the address/command byte.
CS SCLK SDI SDO CLKE = 0 R/W 0 0 0 0 1 0 0 D0 D0 D1 D1 D2 D3 D4 D5 Data Input/Output D2 D3 D4 D5 D6 D6 D7 D7
Address/Command Byte
Figure 9. Input/Output Timing (showing address 0x10)
7
6
LLOOP RAMPLSE X 0
5
RLOOP
4
Reserved Set to "0"
3
Reserved Set to "0" LOOPUP EQ3 0
2
HDB3 RPWDN EQ2 0
1
NLOOP TxHIZ EQ1 0
0
LOS
ADDR
0x10 R/W
Control Register 1 Control Register 2 Equalizer Gain
(EQGAIN)
TAOS AIS X MSB 0
Reserved LOOPDN set to `0" X 0 EQ4 0
Reserved 0x11 R/W set to `0" EQ0 LSB 0 0x12 R 0x13 R/W 0x14
Arbitrary Waveform RAM Address Reserved Set to "0"
Note: All Control Registers initialize to 0x00.
Table 2. Register Map
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2.11.1 Control Register 1: Address 0x10
7 (MSB) TAOS 6 LLOOP 5 RLOOP 4 Reserved Set to "0" 3 Reserved Set to "0" 2 HDB3 1 NLOOP 0 (LSB) LOS
TAOS LLOOP
Transmit All Ones Select When TAOS = 1, all ones are transmitted at the TCLK frequency Local Loopback When LLOOP = 1, data input at TPOS, TNEG (TDATA) is internally looped back and output on RPOS, RNEG (RDATA). TCLK is routed to RCLK, through the jitter attenuator, if activated. Remote Loopback When RLOOP = 1, clock and data recovered by the receiver are sent back through the transmit path and retransmitted. The clock and data are routed through the jitter attenuator, if activated. Reserved - Set Bits 3 & 4 to "0" for proper operation. Setting HDB3 to "1" enables HDB3 encoding and decoding. Network Loopback NLOOP = 1 when a network loopback code has been detected on the received signal. An interrupt will occur when NLOOP changes state unless a "1" is written to NLOOP disabling the interrupt. Loss Of Signal LOS = 1 when the loss of signal criteria have been met (See Receiver Loss of Signal). LOS = 0 when a valid signal is being received. Writing a "1" to LOS disables interrupts due to LOS and the LOS Change indication in bits 5 and 6.
RLOOP
BITS 4:3 HDB3 NLOOP
LOS
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2.11.2 Control Register 2: Address 0x11
7 (MSB) AIS 6 RAMPLSE 5 RSVD 4 LOOPDN 3 LOOPUP 2 RPWDN 1 TxHIZ 0 (LSB) RSVD
AIS
Alarm Indication Signal. AIS = 1 when an all ones pattern is present at the receiver. This bit is reset to "0" by the first read occurring after the AIS condition has cleared. An interrupt will occur when AIS is present unless a "1" is written to AIS disabling the interrupt. When RAMPLSE = 1, output pulse shapes are determined by the codes in the internal, programmable, transmit RAM. Reserved Set to "0" for proper operation. Loop Down In Long Haul mode, setting LOOPDN to "1" causes the data pattern 001... to be repetitively transmitted. Loop Up In Long Haul mode, setting LOOPUP to "1" causes the data pattern 00001... to be repetitively transmitted. Receiver Power Down When RPWDN = 1, the receiver circuitry is powered down, but the transmitter is still active. Transmitter High Impedance When TxHIZ = 1 the transmitter goes to a low-power, high-impedance state
RAMPLSE RSVD LOOPDN
LOOPUP
RPWDN TxHIZ
2.11.3 Equalizer Gain (EQGAIN): Address 0x12
7 (MSB) X 6 X 5 X 4 EQ4 3 EQ3 2 EQ2 1 EQ1 0 (LSB) EQ0
EQ[4:0]
The receive equalizer gain settings are broken down into 20 segments and provided at the five LSBs of this register, EQ4 - EQ0. 00001 corresponds to -2 dB, 10100 corresponds to -40 dB. The three MSBs are don't cares.
2.11.4 Arbitrary Waveform RAM Address (RAM): Address 0x13
7 (MSB) RAM.7 6 RAM.6 5 RAM.5 4 RAM.4 3 RAM.3 2 RAM.2 1 RAM.1 0 (LSB) RAM.0
RAM[7:0]
Arbitrary Waveform RAM; Onboard RAM is provided so that custom pulse shapes may be downloaded (see Arbitrary Waveform Generation section). Writing the waveform RAM requires first writing the Address/Command Byte with the write bit set (see Figure 10) followed by a data byte which specifies the RAM address to be written. Following these two bytes is a third byte that represents the waveform coefficient to be stored in the target address. There are 42 RAM byte locations (numbered h00 to h29).
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Reading the control/status registers returns their current status or setting. Control Register 1 (0x10)) outputs the status of NLOOP and LOS. Additionally, 5, 6, and 7 encoded as shown in Tables 3.
2.13
Power On Reset / Reset
2.12
Interrupts
An interrupt will occur (INT pulls low) in response to a change in the LOS, AIS or NLOOP bits. The interrupt is cleared when the host processor writes a "1" to the respective bit in the control register. Writing a "1" to LOS or NLOOP over the serial interface has three effects: 1) The current interrupt on the serial interface will be cleared. (Note that simply reading the register bits will not clear the interrupt). Output data bits 5, 6 and 7 will be reset as appropriate. Interrupts for the corresponding LOS and NLOOP will be prevented from occurring.
Upon power-up, the IC is held in a static state until the supply crosses a threshold of approximately 3 Volts. When this threshold is crossed, the device will delay for about 10 ms to allow the power supply to reach operating voltage. After this delay, calibration of the transmit and receive sections commences. Because power up conditions can vary considerably, it is recommended that the device be reset after the power supply has stabilized to ensure a known initial operational condition. The internal frequency generators can be calibrated only if a reference clock is present. The reference clock for the transmitter is provided by TCLK. The reference for the receiver is either the crystal oscillator or MCLK. If both the oscillator and MCLK are active, MCLK will be used as the reference source. The initial calibration should take less than 20 ms after pulses are input to the receiver. In operation, the device is continuously calibrated, making the performance of the device independent of power supply or temperature variations. The continuous calibration function forgoes any requirement to reset the line interface when in operation. However, a reset function is available which will reinitiate calibration and clear all registers and clear the Network Loopback function. In Host Mode, a reset is initiated by simultaneously writing RLOOP and LLOOP to the register. The reset will set all registers to "0" and initiate a calibration. A reset will also set LOS high in the Short Haul configuration. In Hardware Mode, the CS61318 is reset by simultaneously setting RLOOP and LLOOP high for at least 200 ns. Hardware reset will clear Network Loopback functionality
2) 3)
Writing a "0" to either LOS or NLOOP enables the corresponding interrupt for LOS and NLOOP.
Bits Status Mode 7 0 0 0 0 1 1 1 1 6 0 0 1 1 0 0 1 1 5 0 Reset has occurred, or no program input 1 RLOOP active 0 LLOOP active 1 LOS has changed state since last Clear LOS occurred 0 TAOS active 1 NLOOP has changed state since last Clear NLOOP occurred 0 TAOS and LLOOP active 1 LOS and NLOOP have both changed state since last Clear NLOOP and Clear LOS
2.14
Power Supply
Table 3. Control Register 1 (0x10) Decoding
The device operates from a single +5 Volt supply. Separate pins for transmit and receive supplies provide internal isolation. These pins should be decou15
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pled to their respective grounds. TV+ must not exceed RV+ by more than 0.3 V. Decoupling and filtering of the power supplies is crucial for the proper operation of the analog circuits in both the transmit and receive paths. A 47F tantalum and 1.0F mylar or ceramic capacitor should be connected between TV+ and TGND, and a 0.1F mylar or ceramic capacitor should be connected between RV+ and RGND. Place capacitors as closely as possible to their respective power supply pins. Wire-wrap breadboarding of the line interface is not recommended because lead resistance and inductance serve to defeat the function of the decoupling capacitors.
E1 Arbitrary Waveform Example
Figure 10. Phase Definition of Arbitrary Waveform
The CS61318 divides the 488 ns UI into 14 uniform phases (34.9 ns each), and uses the phase information written for all 14 phases of each UI. When transmitting pulses, the CS61318 will add the amplitude information from the prior two symbols with the amplitude of the first UI of the current symbol before outputting a signal on TTIP/TRING. Therefore, a mark preceded by two spaces will be output exactly as the mark is programmed. However, when one mark is preceded by marks, the first portion of the last mark may be modified. With AMI data, where successive pulses have opposite polarity, the undershoot tail of one pulse will cause the rising edge of the next mark to rise more quickly, as shown in Figure 11.
3 ARBITRARY WAVEFORM GENERATION
In addition to the predefined pulse shapes, the user can create custom pulse shapes under the Host Mode operation. This flexibility allows the board designer to accommodate non-standard cables, EMI filters, protection circuitry, etc. The arbitrary pulse shape of mark (a transmitted "1") is specified by describing it's pulse shape across three Unit Intervals (UIs). This allows, for example, the long-haul return-to-zero tail to extend into the next UI, or two UIs, as is required for isolated pulses. Each UI is divided into multiple phases, and the users defines the amplitude of each phase. The waveform of a space (a transmitted "0") is fixed at zero volts. Examples of the phases are shown in Figure 10. In all cases, to define an arbitrary waveform, the user writes to the Waveform Register either 36, 39 or 42 times (12, 13 or 14 phases per UI for three UIs). The phases are written in the order: UI1/phase1, UI1/phase2, ... , UI1/phase14, UI2/phase1, ... , UI2/phase14, UI3/phase1, ... , UI3/phase14.
Figure 11. Example of Summing of Waveforms
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The amplitude of each phase is described by a 7-bit, 2's compliment number, where a positive value describes pulse amplitude, and a negative value describes pulse undershoot. The positive full value is hex 3F. The negative full value is hex 40. For E1 shielded twisted pair, the typical output voltage is 27 mV/LSB. All voltages are peak voltages across the TTIP and TRING outputs. Using the circuits given in the Applications section of the data sheet, the output impedance of the device will be approximately equal to the impedance of the line. This means that the voltage on the transformer secondary will be twice the values stated above. Note that although the full scale digital input is 3F, it is recommended that full scale output voltage on the transformer primary be limited to
Diagnostic Mode
2.4 Vpk. At higher output voltages, the driver may not drive the requested output voltage. The amplitude information for all phases is written via the serial-port to Arbitrary Waveform RAM registers (see Arbitrary Waveform RAM register for description). Each phase amplitude is written as an eight-bit byte, where the first phase of the symbol is written first. The contents of the Arbitrary Waveform RAM can be verified by performing a read operation. Reading the waveform RAM requires first writing the Address/Command Byte with the R/W bit set to "1" (see Figure 10) followed by a data byte which specifies the RAM address to be read. On subsequent SCLK's the contents of the specified RAM location will be clocked out on SDO.
Availability (Note 1) H/W Host Yes Yes Yes Yes No Yes Yes No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Host Mode (Note 2) Maskable No No Yes No No No Yes Yes No
Loopback Modes Local Loopback (LLOOP) Remote Loopback (RLOOP) In-band Network Loopback (NLOOP) Internal Data Pattern Generation and Detection Transmit All Ones (TAOS) In-band Loop-up/down Code Generator Error Detection Bipolar Violation Detection (BPV) Alarm Condition Monitoring Receive Loss of Signal Monitoring (LOS) Receive Alarm Indication Signal Monitoring (AIS) Other Diagnostic Reports Receive Line Attenuation Indicator (LATN)
Table 4. CS61318 Diagnostic Mode Availability Notes: 1. In Hardware Mode the Diagnostic Modes are selected by directly setting the pins on the device; in Host Mode, the appropriate register bits are written for Diagnostic Modes. 2. In Host Mode the interrupts can be masked by writing a "1" to the LOS bit; there is no masking in the Hardware Mode.
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CS61318
Turns ratio: 120 Twisted Pair Application Turns ratio: 75 Twisted Pair Application
1:2 step-up transmit, 1:1 receive 1:1.58 step-up transmit, 1:1 receive
Table 5. Transformer Specification Turns Ratio(s) 1:1CT Manufacturer Pulse Engineering Valor Schott Valor Schott Pulse Engineering Valor Schott Valor Schott Pulse Engineering Valor Pulse Engineering Pulse Engineering Valor Pulse Engineering Pulse Engineering Part Number PE-64936 PT5008 67130840 ST5085 31187 PE-65351 PT5004 617130850 ST5086 31188 PE-68678 ST5162 PE-68877 T-1068 ST5173 T-1031 T-1229 Package Type 1.5 kV, through-hole, single
1.5 kV, surface mount, single 1.5 kV, through-hole, single
1:2CT
1.5 kV, surface mount, single 1.5 kV, surface mount, dual 1.5 kV, surface mount, dual extended temp. 1.5 kV, surface mount, quad port 3 kV, surface mount, dual 1.5 kV, through hole, single
1:1CT 1:2CT
1:1.58 CT
Table 6. Recommended Tranformers for the CS61318
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4 PIN DESCRIPTION
MCLK TCLK TPOS/TDATA TNEG/UBS MODE RNEG/BPV RPOS/RDATA RCLK XTALIN XTALOUT JASEL LOS TTIP TGND TAOS/CLKE LLOOP/SCLK RLOOP/CS SDO SDI NLOOP/INT RGND RV+ RRING RTIP LATN NC TRING TV+
MCLK TCLK TPOS/TDATA TNEG/UBS MODE RNEG/BPV RPOS/RDATA RCLK XTALIN XTALOUT JASEL LOS TTIP TGND
5 6 7 8 9 10 11 12 13 14 15 16 17 18 top view 4 3 2 1 28 27 26 25 24 23 22 21 20 19
TAOS/CLKE LLOOP/SCLK RLOOP/CS SDO SDI NLOOP/INT RGND RV+ RRING RTIP LATN NC TRING TV+
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4.1 Power Supplies
TV+ - Power Supply, Transmit Driver, Pin 15.
Power supply for the transmit driver; typically +5 Volts.
TGND - Ground Transmit Driver, Pin 14.
Power supply ground for the transmit driver; typically 0 Volts.
RV+ - Power Supply, Pin 21.
Power supply for all subcircuits except the transmit driver; typically +5 Volts.
RGND - Ground, Pin 22.
Power supply ground for all subcircuits except the transmit driver; typically 0 Volts.
4.2
Oscillator
XTALIN, XTALOUT - Crystal Connections, Pins 9 and 10.
A 8.192 MHz crystal can be connected across these pins. This oscillator provides the reference frequency for the LIU if MCLK is not provided. The load capacitance presented to the crystal by these pins should be approximately 19pF (IC and package, when soldered into a circuit board). The jitter attenuator may be disabled by tying pin 9 to RV+ through a 1k resistor, and floating XTALOUT. When pin 9 has no clock input, a clock must be supplied to the MCLK pin. Alternatively an external 8.192 MHz clock can be driven into pin 9, and the jitter attenuator circuit will operate. If MCLK is provided, and XTALIN is tied low or floated, the jitter attenuator will be enabled.
4.3
Control
MCLK - Master Clock Input, Pin 1.
Either MCLK or the crystal oscillator provide the master frequency reference for the CS61318. If both MCLK and the crystal oscillator are present, the oscillator is ignored. MCLK should be 2.048 MHz for E1 operation. In a Loss of Signal state, RCLK will be derived from MCLK, through the jitter attenuator, if active. If MCLK is not provided, the jitter attenuator will hold the RCLK frequency in a Loss of Signal state. MCLK should be grounded if it is not used.
MODE - Mode Select Input, Pin 5.
Setting the MODE pin high puts the CS61318 into Host Mode where the device is controlled by a microprocessor, via a serial port. Setting the MODE pin low, configures the part for hardware mode control where control and status are provided through dedicated pins. The MODE pin is internally pulled down placing the part in Hardware Mode when this pin is left floating. Tying the MODE pin to RCLK places the chip in Hardware Mode and enables the HDB3 encoder/decoder (provided that coder mode has been enabled; see the description for TNEG/UBS pin).
TAOS - Transmit All Ones Select Input, Pin 28 (Hardware Mode).
Setting TAOS to logic 1 causes continuous ones to be transmitted at the TCLK frequency. When TAOS is high, TPOS and TNEG (TDATA) are not output at the TTIP/TRING pins. TAOS is overridden by Remote Loopback. Setting TAOS, LLOOP, and RLOOP high simultaneously enables Network Loopback detection.
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LLOOP - Local Loopback Input, Pin 27(Hardware Mode).
Setting LLOOP to a logic 1 internally routes the transmitter input to the receiver output. If TAOS is low, the signal being output from the transmitter will be internally routed to the receiver inputs allowing nearly the entire chip to be tested. If TAOS and LLOOP are set high at the same time, the local loopback will occur at the jitter attenuator (excluding the transmit and receive circuitry) and the transmitter will transmit all ones. Simultaneously setting RLOOP and LLOOP high while TAOS is low resets the CS61318. Simultaneously setting RLOOP, LLOOP and TAOS high enables Network Loopback detection.
RLOOP - Remote Loopback Input, Pin 26 (Hardware Mode).
Setting RLOOP to a logic 1 causes the received signal to be passed through the jitter attenuator (if active) and retransmitted onto the line. The internal encoders/decoders will be bypassed in Remote Loopback. Simultaneously setting RLOOP and LLOOP high while TAOS is low resets the CS61318. Simultaneously setting RLOOP, LLOOP and TAOS high enables Network Loopback detection.
JASEL - Jitter Attenuator Select, Pin 11.
If the jitter attenuator is enabled (crystal oscillator active, or XTALIN tied low or floated with MCLK provided), setting JASEL high places the jitter attenuator in the receive path; setting JASEL low places the jitter attenuator in the transmit path.
NC - No Connect, Pin 17.
The input voltage to this pin does not effect normal operation.
4.4
Status
LOS - Loss Of Signal Output, Pin 12.
LOS goes high when 175 consecutive zeros are received. LOS returns low when the ones density reaches 12.5% (based on 175 consecutive bit periods, starting with a one and containing less than 100 consecutive zeros, as prescribed in ITU-T G.775). If LOS is true, and the jitter attenuator is in the receive path, RCLK will smoothly transition to MCLK if provided; RCLK will retain the frequency prior to LOS if MCLK is grounded. If the jitter attenuator is NOT in the receive path, RCLK will become the reference clock frequency (MCLK) if provided, or the crystal oscillator.
NLOOP - Network Loopback Output, Pin 23 (Hardware Mode).
NLOOP goes high when a 00001 pattern is received for five seconds putting the CS61318 into network (remote) loopback. NLOOP is deactivated upon receipt of a 001 pattern for five seconds, or by selection of LLOOP or RLOOP.
LATN - Line Attenuation Indication Output, Pin 18.
LATN is an encoded output that indicates the receive equalizer gain setting in relation to a five RCLK cycle period. If LATN is high for one RCLK cycle, the equalizer is set for 9.5 dB gain, two cycles = 19.5 dB gain, three cycles = 28.5 dB gain, four cycles = 0 dB. LATN may be sampled on the rising edge of RCLK.
4.5
Serial Control Interface
INT - Interrupt Output, Pin 23 (Host Mode).
INT pulls low to flag the host processor when NLOOP, AIS or LOS changes state. INT is an open drain output and should be tied to the supply through a resistor.
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SDI - Serial Data Input, Pin 24 (Host Mode).
Data input to the on-chip register is sampled on the rising edge of SCLK. Note: this pin should be tied to GND during Hardware Mode.
SDO - Serial Data Output, Pin 25 (Host Mode).
Status and control information are output from the on-chip register on SDO. If CLKE is high, SDO is valid on the rising edge of SCLK. If CLKE is low, SDO is valid on the falling edge of SCLK. SDO goes to a high-impedance state when the serial port is being written to, or after bit D7 is output or CS goes high (whichever occurs first). Note: this pin should be tied to GND during Hardware Mode.
CS - Chip Select, Pin 26 (Host Mode).
The serial interface is accessible when CS transitions from high to low.
SCLK - Serial Clock Input, Pin 27 (Host Mode).
SCLK is used to write or read data bits to or from the serial port registers.
CLKE - Clock Edge, Pin 28 (Host Mode).
Setting CLKE to logic 1 causes RPOS and RNEG (RDATA) to be valid on the falling edge of RCLK, and SDO to be valid on the rising edge of SCLK. Conversely, setting CLKE to logic 0 causes RPOS and RNEG (RDATA) to be valid on the rising edge of RCLK and SDO to be valid on the falling edge of SCLK.
4.6
Data Input/Output
TCLK - Transmit Clock Input, Pin 2.
The 2.048 MHz transmit clock is input on this pin. TPOS and TNEG or TDATA are sampled on the falling edge of TCLK.
TPOS/TNEG - Transmit Positive Pulse, Transmit Negative Pulse, Pins 3 and 4.
Data input to TPOS and TNEG is sampled on the falling edge of TCLK and transmitted onto the line at TTIP and TRING. An input on TPOS results in transmission of a positive pulse; an input on TNEG results in transmission of a negative pulse. If TNEG, pin 4, is held high for 16 TCLK cycles, the CS61318 reconfigures for unipolar (single pin NRZ) data input at pin 3, TDATA. If pin 4 goes low the CS61318 switches back to two-pin bipolar data input format.
TDATA - Transmit Data, Pin 3.
When pin 4, TNEG/UBS, is held high, pin 3 becomes TDATA, a single-line NRZ (unipolar) data input sampled on the falling edge of TCLK.
UBS - Unipolar / Bipolar Select, Pin 4.
When UBS is held high for 16 consecutive TCLK cycles (15 consecutive bipolar violations) the CS61318 reconfigures for unipolar (single-line NRZ) data input / output format. Pin 3 becomes TDATA, pin 7 becomes RDATA, and pin 6 becomes BPV.
RCLK - Recovered Clock Output, Pin 8.
RCLK outputs the clock recovered from the input signal at RTIP and RRING. In a Loss of Signal state RCLK reverts to the MCLK frequency, or retains the frequency prior to the LOS state, depending on the clocks provided. See the LOS pin description.
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RNEG/RPOS - Receive Negative Pulse, Receive Positive Pulse, Pins 6 and 7.
Recovered data output on RPOS and RNEG is stable and valid on the rising edge of RCLK in Hardware Mode. In Host Mode, CLKE determines the edge of RCLK on which RPOS and RNEG are valid. A positive pulse on RTIP with respect to RRING generates a logic 1 on RPOS; a positive pulse on RRING with respect to RTIP generates a logic 1 on RNEG.
RDATA - Received Data, Pin 7.
Unipolar data (single-line NRZ) data is output on RDATA when pin 4, TNEG/UBS, is held high.
BPV - Bipolar Violation, Pin 6.
When pin 4 is held high, received bipolar violations are flagged by BPV (RNEG) going high along with the offending bit output from RDATA. If the HDB3 encoder/decoder is activated, BPV will not flag bipolar violations resulting from valid zero substitutions.
RTIP,RRING - Receive Tip; Receive Ring, Pins 19,20.
The HDB3 signal received from the line is input via these pins. A 1:1 transformer and appropriate matching resistors are required as shown in the applications section. Data and clock recovered from the signal input on these pins is output via RPOS, RNEG, and RCLK.
TTIP, TRING - Transmit Tip; Transmit Ring, Pins 13,16
These pins are the output of the differential transmit driver. The transformer and matching resistors can be chosen to give the desired pulse height (see Application Schematics).
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CS61318
5 PACKAGE DIMENSIONS
28 PIN PLASTIC (PDIP) PACKAGE DRAWING
D E 1 SEATING PLANE e b A A1 b1 L
c eA
TOP VIEW
SIDE VIEW
BOTTOM VIEW
INCHES DIM A A1 b b1 c D E e eA L MIN 0.155 0.020 0.014 0.040 0.008 1.435 0.540 0.095 0.600 0.125 0 MAX 0.200 0.040 0.022 0.065 0.015 1.465 0.560 0.105 0.625 0.150 15
MILLIMETERS MIN MAX 3.94 5.08 0.51 1.02 0.36 0.56 1.02 1.65 0.20 0.38 36.45 36.83 13.72 14.22 2.41 2.67 15.24 15.87 3.18 3.81 0 15
1. Positional tolerance of leads shall be within 0.25 mm (0.010 in.) at maximum material condition, in relation to seating plane and each other. 2. Dimension eA to center of leads when formed parallel. 3. Dimension E does not include mold flash.
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28L PLCC PACKAGE DRAWING
e D2/E2
E1 E
B
D1 D A
A1
INCHES DIM A A1 B D D1 D2 E E1 E2 e MIN 0.165 0.090 0.013 0.485 0.450 0.390 0.485 0.450 0.390 0.040 MAX 0.180 0.120 0.021 0.495 0.456 0.430 0.495 0.456 0.430 0.060
MILLIMETERS MIN MAX 4.043 4.572 2.205 3.048 0.319 0.533 11.883 12.573 11.025 11.582 9.555 10.922 11.883 12.573 11.025 11.582 9.555 10.922 0.980 1.524
JEDEC #: MS-018
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CS61318
6 APPLICATIONS
+5V + 33 F RGND 28 Control & Monitor 1 12 6 18 11 CLKE
MCLK
0.1 F
+
1.0 F TGND
21 RV+
15 TV+
SCLK
CS
27 26 23 24 25
P
LOS BPV LATN JASEL
INT SDI SDO
Serial Port
RV+ 1 k 5 MODE 7 6 Frame Format Encoder/ Decoder 8 3 4 2 9 10 RPOS RNEG
CS61318 IN HOST MODE
RTIP
19
R1
1 0.47 F
2 RECEIVE
R2 RRING 20
LINE 5 T1 1:1 6
RCLK
TPOS TNEG TCLK XTALIN XTALOUT RGND 22 TGND 14 TRING TTIP
16 13 R4 R3 0.47 F 2 6 T2 1:N 1 5 TRANSMIT LINE
Figure 12. CS61318 Host Mode Operation E1 75 Coaxial Cable R1 () R2 () R3 () R4 () T2 37.5 37.5 15 15 1:1.58 E1 120 Twisted Pair 60 60 15 15 1:2
NOTE: The 0.47F capacitor between R1 & R2 may be omitted if common mode noise is not an issue. NOTE: The optional 0.47F DC blocking cap eliminates DC saturation current through T2
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+5V + 33 F RGND 28 1 Control & Monitor 26 27 12 23 11 5 TAOS MCLK RLOOP LLOOP LOS NLOOP JASEL MODE SD I SDO 24 25 0.1 F + 1.0 F TGND
21 RV+
15 TV+
7 6 Frame Format Encoder/ Decoder 8 3 4 2
RPOS RNEG RCLK TPOS TNEG TCLK
CS61318 IN HARDWARE MODE
RTIP
19 R1 R2
1 0.47 F
2 RECEIVE LINE
RRING
20
5 T1 1:1
6
R3 0.47 F 16 TRING 13 6 R4 RGND 22 TGND 14 T2 1:N 5 TTIP 2 1 TRANSMIT LINE
9 10
XTALIN XTALOUT
Figure 13. Hardware Mode Configuration
E1 75 Coaxial Cable R1 () R2 () R3 () R4 () T2 37.5 37.5 15 15 1:1.58
E1 120 Twisted Pair 60 60 15 15 1:2
NOTE: The 0.47F capacitor between R1 & R2 may be omitted if common mode noise is not an issue. NOTE: The optional 0.47F DC blocking cap eliminates DC saturation current through T2
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